1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device such as a DRAM with a built-in buffer circuit receiving an external signal.
2. Description of the Background Art
FIG. 6 is a block diagram showing an entire structure of a conventional DRAM. Referring to FIG. 6, a clock signal generation circuit 101 responds to externally applied ZRAS and ZCAS signals of a TTL level to generate a clock signal of a CMOS level. An externally applied ZWE signal of a TTL level and a clock signal from clock signal generation circuit 101 are applied to a gate circuit 102. In response, gate circuit 102 provides a control signal to an input buffer 103 and an output buffer 104. An address buffer circuit 110 includes a row address buffer circuit that provides a row address signal INX of a CMOS level and a column address buffer circuit that provides a column address signal INY of a CMOS level according to externally applied address signals A.sub.0, A.sub.1, . . . A.sub.n of a TTL level. A row address signal is applied to a row decoder 105, and a column address signal is applied to a column decoder 106 after being latched in a latching circuit 111. Row decoder 105 decodes a row address signal to specify a row address of memory cell array 109. Column decoder 106 decodes a column address signal to specify a column address of memory cell array 109.
Input buffer 103 receives data of a TTL level. An input/output control circuit 108 writes data applied via input buffer 103 into an addressed memory cell, or reads out data from an addressed memory cell. The read out data is outputted via an output buffer 104 from a driver 107. Output buffer 104 is activated by an externally applied ZOE signal of a TTL level. Here, in a TTL level, the potential is 0.8 V at a L level, and 2.0 V at a H level. In a CMOS level, the potential is 0 V at a L level and power supply potential of Vcc at a H level.
FIG. 7 is a circuit diagram showing an example of a row address buffer circuit of FIG. 7.
Referring to FIG. 7, a power supply reset signal generation circuit 1 is included in a clock signal generation circuit 101 of FIG. 6. Power supply reset signal generation circuit 1 generates a power-on reset (ZPOR) signal in response to the power turned on. More specifically, power supply reset signal generation circuit 1 includes a resistor R2 and a capacitor C3 connected between power supply Vcc and ground, and CMOS inverters 4 and 5 connected to the node thereof. The ZPOR signal of a CMOS level provided from power supply reset signal generation circuit 1 is inverted by CMOS inverter 6 to be applied to one input terminal of a CMOS NOR gate 51. NOR gate 51 has a ZRAS signal applied to the other input terminal, and prevents a ZRAS signal from being fetched inside until the power is turned on. NOR gate 51 responds to a ZPOR signal of a L level to provide a ZRAS signal. The output of NOR gate 51 is delayed by inverters 8 and 9 to be output as an activation signal .phi.1. Activation signal .phi.1 is applied to a row address buffer circuit 20 and to a delay circuit 10. Delay circuit 10 includes CMOS inverters 11 and 14, a pMOS capacitor 12, and an nMOS capacitor 13. Delay circuit 10 delays activation signal .phi.1 for a predetermined time. This delayed output is inverted by a CMOS inverter 15 to be provided to row address buffer circuit 20 as a delayed activation signal .phi.2 of a CMOS level.
Row address buffer circuit 20 forms a latching circuit having the inputs and outputs of two inverters 20a and 20b connected alternately. One inverter 20a includes pMOS transistors 21 and 22, and nMOS transistors 23, 24, 25 and 26. The other inverter 20b includes pMOS transistors 27 and 28, and nMOS transistors 29, 30, 31 and 32. Power supply +V is applied to the sources of pMOS transistors 21 and 22 of one inverter 20a. Activation signal .phi.1 is applied to respective gates of pMOS transistor 21 and nMOS transistor 23. PMOS transistors 21 and 22 have their drains connected to the drain of nMOS transistor 23 via a node A. A ZINX1 signal is outputted from node A. NMOS transistor 23 has its source connected to the drains of nMOS transistors 24 and 26. A delayed activation signal .phi.2 is applied to the gate of the nMOS transistor 24. NMOS transistor 24 has its source connected to the drain of nMOS transistor 25 via a node N, and an external row address signal 1 is applied to the gate thereof. NMOS transistors 25 and 26 have their sources grounded. PMOS transistor 22 and nMOS transistor 26 have their gates connected to the output of the other inverter 20b.
PMOS transistors 27 and 28 of the other inverter 20b have their sources connected to power supply +V. Activation signal .phi.1 is applied to the gates of pMOS transistor 28 and nMOS transistor 29. PMOS transistors 27 and 28 have their drains connected to the drain of nMOS transistor 29 via a node B. A INX1 signal is output from node B. NMOS transistor 29 has its source connected to respective drains of nMOS transistors 30 and 32. NMOS transistor 30 has its source connected to the drain of A nMOS transistor 31. A delayed activation signal .phi.2 is applied to the gate of NMOS transistor 30. nMOS transistor 31 has its gate grounded, and nMOS transistors 31 and 32 have their sources grounded. A plurality of row address buffer circuits 20 are provided corresponding to address signals A.sub.0, A.sub.1, . . . , A.sub.n.
FIG. 8 is a timing chart for describing the operation of FIG. 7.
The operation of row address buffer circuit 20 of FIG. 7 will be described with reference to FIG. 8. When the power is turned on as shown in FIG. 8(a), the output ZPOR signal of power supply reset signal generation circuit 1 is rendered to a H level from a L level as shown in (b). When the power supply potential becomes Vcc from 0 V at time t0, the input of inverter 4 via resistor R2 attains a H level to be outputted via inverters 4 and 5, whereby ZPOR signal attains a H level. When ZPOR signal attains a H level, this signal of a H level is inverted by inverter 6 to cause one input terminal of NOR gate 51 gate 51 to attain a L level. In response to the voltage level of a ZRAS signal shown in (c), NOR gate 51 generates a signal. When ZRAS signal attains a L level from a H level at time t1, activation signal .phi.1 attains a H level as shown in (d). At time t2 determined by delay circuit 10, delayed activation signal .phi.2 attains a L level as shown in (e).
When an external row address signal 1 of a H level is applied during the time period of time t3-t4 as shown in (f), the row address buffer circuit 20 provides an INX1 signal of a L level and a ZINX1 signal of a H level as shown in (g), whereby the internal row address attains a H level.
The operation of row address buffer circuit 20 will be described in detail hereinafter. An external row address signal 1 of a TTL level is applied to the gate of nMOS transistor 25 of one inverter 20a. Since the H level is 2 V and the L level is 0.8 V in a TTL level, the threshold potential which is the boundary of a L level and a H level of a TTL level is 1.4 V. The threshold voltage is adjusted by differentiating the size of nMOS transistors 26 and 32 so that ZINX1 signal attains a L level and INX1 signal attains a H level when external row address signal 1 is greater than 1.4 V. When activation signal .phi.1 attains a L level, node A of inverter 20a and node B of inverter 20b are both precharged to the level of power supply potential vcc. Activation signal .phi.1 attains a H level, and one of INX1 signal and ZINX1 signal, which are the outputs of the latch formed by inverters 20a and 20b, is determinated at a L level according to the signal intensity of the external row address signal 1.
Referring to FIG. 8(f), the voltage of external row address signal 1 from time t3 to t4 is 2.0 V which is a H level of TTL, indicating the case where a H address is inputted. Assuming that internal power supply potential Vcc is 3.3 V, activation signal .phi.1 attains a L level of 0 V until time t1', and nodes A and B are precharged to 3.3 V via pMOS transistors 21 and 28. When activation signal .phi.1 rises from 0 V to 3.3 V, pMOS transistors 21 and 28 are turned off. Since delayed activation signal .phi.2 attains a H level of 3.3 V, nMOS transistors 24 and 30 are turned on, whereby nMOS transistors 25 and 31 connected in series to nMOS transistors 24 and 30 conduct. The positive charge in node A is discharged so that the potential of node A approximates 0. As a result, the conductance of pMOS transistor 27 increases to turn on pMOS transistor 27, and the conductance of nMOS transistor 32 is reduced to turn off nMOS transistor 32. Thus, node B becomes 3.3 V. INX1 signal which is an output of inverter 20b is applied to inverter 20a, whereby a positive feedback is applied. ZINX1 signal becomes 0 V, and the latch output is determinated so that INX1 signal becomes 3.3 V.
The time required for the output of the latch to be ascertained depends upon the time required for drawing out the positive charge that is precharged in node A. The current flowing to nMOS transistors 24 and 25 is I when node A is discharged via nMOS transistors 23-25. The ON resistance between the source and drain of nMOS transistor 25 receiving an external row address signal 1 of 2 V at its gate is R1, and the on resistance is R0 when the source potential is 0 V and the gate voltage is 3.3 V. When the gate voltage of the nMOS transistor is reduced, the ON resistance between the source and drain is increased, so that the following equation (1) is established. EQU R1&gt;0 (1)
Therefore, the potential of node N which is the source potential of nMOS transistor 24 is raised by IxR1. When the substrate potential of the nMOS transistor is 0 V, a back-bias of -IxR1 is applied across nMOS transistor 24, whereby the threshold value of nMOS transistor 24 rises due to a body effect. Although activation signal .phi.2 of 3.3 V is applied to the gate of nMOS transistor 24, source-drain ON resistance R2 becomes greater than R0 as shown in the following equation (2). EQU R2&gt;R0 (2)
By a body effect due to the potential rise of node N, the ON resistance between the source and drain of nMOS transistor 24 is increased. As a result, the discharging speed of node A is reduced to delay an output of an internal row address.
FIG. 9 is a circuit diagram showing a conventional column address buffer circuit. Referring to FIG. 9, an externally applied ZCAS signal of a TTL level is inverted by an inverter 41 to be applied to one input terminal of a CMOS NAND gate 42. A ZPOR signal is applied from a power supply reset signal generation circuit 1 to the other input terminal of NAND gate 42. NAND gate 42 functions to prevent output of a ZCAS signal until the power supply rises. The output of NAND gate 42 is inverted by a CMOS inverter 43 to be applied to one input terminal of a CMOS NAND gate 44 as an activation signal .phi.3. An external column address signal 1 of a TTL level is applied to the other input terminal of NAND 44. NAND gate 44 responds to activation signal .phi.3 to output an external column address signal 1. The output thereof is inverted by an inverter 45 to be provides as an internal column signal. A plurality of column address buffer circuits are provided corresponding to address signals A.sub.1, A.sub.2, . . . A.sub.n.
FIG. 10 is a timing chart for describing an operation of the column address buffer of FIG. 9. When the power supply voltage is powered on from 0 V to Vcc at time t0 as shown in (a), a ZPOR signal outputted from power supply reset signal generation circuit 1 is pulled up to a H level from a L level, as shown in (b), to be applied to NAND gate 42. Because ZCAS signal attains a H level of 2 V at a TTL level in a standby state, NAND gate 42 takes the logical product of an inversion signal of inverter 41 and a ZPOR signal, and does not accept an external input prior to the power being turned on. More specifically, because ZPOR signal attains a L level until power is turned on, NAND gate 42 does not accept a ZCAS signal.
After the power is turned on, when ZCAS signal is pulled down to a L level from a H level at time t1, activation signal .phi.3 attains a H level as shown in (d), whereby NAND gate 44 accepts an input external column address signal 1. FIG. 10(e) shows the case where external column address signal 1 attains a H level. When activation signal .phi.3 is pulled up to a H level, the address buffer output INY1 attains a H level as shown in (f). Here, the first stage of the column address buffer circuit of FIG. 9 is formed by an inverter 41. In the conventional column address buffer circuit shown in FIG. 9, a through current will be conducted in inverter 41 when ZCAS signal attains an intermediate potential between 0 V and power supply voltage Vcc even before the power is turned on.
As described above, a conventional row address buffer circuit is a latching type having the inputs and outputs of two inverters 20a and 20b connected to each other as shown in FIG. 7. There was the problem that the time for a latched output to be ascertained is delayed.
Furthermore, because the column address buffer circuit of FIG. 9 has the buffer means receiving a ZCAS signal of a H level formed by inverter 41 and NAND gate 42, there is a possibility of a through current flowing in inverter 41 even when the power is not yet turned on.
In recent semiconductor memory devices, the memory capacity is increased from 16M bits to a greater level such as 64M bits and 256M bits. In response, there is a greater number of address signals, resulting in increase of the address pins. Furthermore, the number of data input buffers is increased due to multi-bit data. It is necessary to increase the integration density according to increase in the memory capacity.
There are cases when a CMOS NOR gate or a CMOS NAND gate is used as a buffer. Comparing a NOR gate with an NAND gate having the same driving capability, an NAND gate is smaller in size. Although the usage of a NOR gate and a NAND gate has respective merits and demerits, a NAND gate is preferably used in order to improve the integration density.